1. Field of the Invention
The present invention relates to the simulation of a circuit and, in particular, to the simulation of a dual processor circuit.
2. Background
Normally, there is a significant time-gap between electronic circuit design and high-volume production of the newly designed circuit. Prior to investing in costly mass production, manufacturers test the circuit for assurance that the circuit design is valid. A physical limitation to the testing of circuits is imposed by the high cost of building circuits on an individual scale. To overcome the cost of low-volume circuit production, designers have turned to computer simulation of newly designed circuits to provide low-cost, robust testing of new circuit designs.
Communication between computer simulators commonly involves using temporary files. One simulator allocates a temporary file, writes to it and then deallocates it. The second simulator allocates that same temporary file, reads the data to be communicated and deallocates it. Consequently, communication between two simulators entails a long instruction chain resulting in poor performance. Other common methods of communicating between simulators are pipe and buffer structures. Managing these structures also entails overhead. Furthermore, traditional simulators do not simulate the communication capabilities present in the underlying hardware. For example, circuit components don't typically communicate via a temporary file. What is needed is a simulator of a dual processor circuit that will have better performance than traditional simulators. Furthermore, what is needed is a simulator that accurately simulates the communication operations existing in the underlying electronic circuit.